In a semiconductor integration circuit, it has been difficult to obtain a stable current against a process variation, a power supply voltage variation, and a temperature variation in a simple circuit configuration. For example, as shown in FIG. 1, a constant current circuit disclosed in Patent Literature 1 (JP 2008-052639A) includes a band gap reference circuit 1, a current outputting circuit 2, an inverting circuit 3, and a level shifter 4. The band gap reference circuit 1 includes PMOS transistors P1 and P2, NMOS transistors N1 to N3, a resistance R1, and diodes D1 and D2. The NMOS transistor N3 serves as a variable resistance for feedback. The level shifter 4 includes PMOS transistors P3 and P4. The inverting circuit 3 includes PMOS transistors P5 and P6, and an NMOS transistor N4. The inverting circuit 3 serves as an error amplifying circuit. The current outputting section 2 includes a PMOS transistor P7.
When the value of the resistance R1 varies due to the process variation, the resistance value of the NMOS transistor N3 serving as the variable resistance for feedback is changed by the inverting circuit 3 serving as the error amplifying circuit, to suppress a variation of an output current I4 from the output transistor P7. Here, a basic current of the current I4 flowing through the output transistor P7 is given by the following equation (1):
                              I          4                =                  m          ⁢                      kT                          qR              1                                                          (        1        )            where m is a constant (uniquely determined based on a mirror ratio of P1 to P2, and an area ratio of D1 to D2), k is the Boltzmann constant (1.38×10−23 [J/K]), T is an absolute temperature [K], q is elementary charge (1.602×10−19 [C]), and R1 is the value of the resistance R1 [•].
Here, the resistance R1 is required to have a temperature characteristic proportional to the absolute temperature T to reduce a temperature dependency of the current I4. That is, since a condition that “T/R1” in the equation (1) is constant needs to be satisfied to reduce the temperature dependency, the semiconductor manufacturing process is restricted.
In addition, operation points of the inverting circuit 3 serving as the error amplifying circuit and of the NMOS transistor N3 serving as the variable resistance for feedback are difficult to be set and, therefore, the operation points easily vary due to the variation of transistors and the like. Accordingly, the amount of feedback is not stable. Here, it should be noted that the term of “kT/q” in the equation (1) is called a thermal voltage in the semiconductor engineering. The thermal voltage is proportional to the absolute temperature T, and has the following voltage values at the respective temperatures:
−40 [° C.] (233 [K]) 20 [mV]
+27 [° C.] (300 [K]) 26 [mV]
+150 [° C.] (423[K]) 36 [mV]